1. Field of the Invention
The present invention relates in general to a semiconductor technology. More particularly, it relates to a method of forming a shallow trench isolation (STI) structure.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions thereof and preventing carriers from penetrating the substrate to neighboring devices.
Among different element isolation techniques, LOCOS and shallow trench isolation manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure. In FIG. 1, a pad oxide layer and a silicon nitride layer (not shown) are formed on a silicon substrate 10. The silicon nitride layer and the pad oxide layer are patterned by lithography and etching, and a trench is then formed in the substrate 10 by etching using the silicon nitride layer as a mask. A liner oxide layer 14 is formed by thermal oxidation on the surface of the trench. Chemical vapor deposition (CVD) oxide layer is deposited and filled into the trench. The excess oxide layer over the silicon nitride layer is removed by chemical mechanical polishing (CMP) to complete the shallow trench isolation structure 16. The silicon nitride layer arid the pad oxide layer are then removed.
Because the property of the element isolation structure 16 is similar to that of the pad oxide layer and liner oxide layer 14, when etching liquid is used to remove pad oxide layer, the element isolation structure 16 is inevitably etched so that the liner oxide layer 14 at the top corner 20 of the trench develops a sharp edge, increasingly attracting the focus of the electric field, hence the the insulating properties of the top corner 20 degrades, resulting in abnormal element characteristics.
Moreover, the etching used for forming the trench in the substrate 10 and the thermally grown liner oxide layer 14 induce stresses into the substrate 10. For example, the stresses concentrate at the top corner 20 and bottom corner 22 of the trench, resulting in inducing leakage current. In addition, more operation time is required for growing liner oxide by thermal oxidation, thus reducing the throughput. Moreover, since typical semiconductor factories use batch furnaces for thermal oxidation, the thin film uniformity is varied, reducing the reliability of the devices.
Accordingly, an object of the invention is to provide a method of forming a shallow trench isolation structure, wherein a liner oxide layer is formed by wet oxidation using single wafer process at high temperatures to obtain a rounder liner oxide layer at the top corner of the trench and increase the uniformity of the liner oxide layers in each wafer to be fabricated.
Another object of the invention is to provide a method of forming a shallow trench isolation structure, wherein in-situ annealing is performed after the liner oxide growth to release stress and prevent dopant diffusion to the STI structure from the device region.
To achieve these and other advantages, the invention provides a method of forming a shallow trench isolation structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.
The silicon oxide layer has a thickness of about 150xcx9c250 xc3x85 and can be formed at about 1100xcx9c1200xc2x0 C. using hydrogen and oxygen as reaction gases. Moreover, the flow rates of the hydrogen and oxygen are about 10xcx9c16 slm and 5xcx9c8 slm, respectively.
Moreover, the annealing is performed in an atmosphere of nitrogen or nitrous oxide at about 1100xcx9c1200xc2x0 C. for 20xcx9c60 sec. The insulating layer is high density plasma oxide.